1. Field of the Invention
The invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device which includes a plurality of reference cells and which is capable of preventing degradation of the reference cells by switching the reference cells one by one.
2. Description of the Related Art
In a semiconductor memory device such as a flash memory (for instance, a flash electrically erasable and programmable read only memory (EEPROM)) or a ferroelectric memory (for instance, FeRAM), data stored in a selected memory cell is compared to data stored in a reference cell for carrying out desired function.
FIG. 1 is a conventional semiconductor memory device comprised of a flash EEPROM having 16 Mbit. Hereinbelow is explained a structure of the conventional semiconductor memory device with reference to FIG. 1.
As illustrated in FIG. 1, the semiconductor memory device is comprised of a first address buffer 11, a second address buffer 12, an address-transition detecting (ATD) circuit 13, a signal generating circuit 14, a Y-decoder 15, a X-decoder 16, a Y-selector 17, a memory cell array 10, a sense amplifier 18, a reference amplifier 19, a comparator-amplifier 20, an output buffer 21, a reference cell MRD, and a reference cell selector QR1.
The first address buffer 11 receives an address signal Ai (i=0 to 9), and transmits an internal address signal Adi (i=0 to 9) to the ATD circuit 13 and the Y-decoder 15. The second address buffer 12 receives an address signal Ai (i=10 to 19), and transmits an internal address signal Adi (i=10 to 19) to the ATD circuit 13 and the X-decoder 16.
On receipt of the internal address signals Adi from the first and second address buffers 11 and 12, the ATD circuit 13 detects variance in the address signals, and transmits an address-transition detecting signal P0 in the form of a one-shot pulse to the signal generating circuit 14.
The signal generating circuit 14 receives the address-transition detecting signal P0 from the ATD circuit 13, and transmits a control signal P1 in the form of a one-shot pulse to the sense amplifier 18 and the reference amplifier 19. Operation of the sense amplifier 18 and the reference amplifier 19 is controlled by the control signal P1.
The X-decoder 16 decodes the received internal address signals Ad10 to Ad19 for selecting a word line. The X-decoder 16 transmits its output signal to one of word lines W0 to Wm for selecting a word line. A voltage VR is applied to the selected word line.
The Y-decoder 15 decodes the received internal address signals Ad0 to Ad9 for selecting a digit line. The Y-decoder 15 transmits its output signal to one of Y-select lines Y0 to Yn for selecting a Y-select line. A voltage VY is applied to the selected Y-select line.
The memory cell array 10 includes a plurality of memory cells MC00 to MCnm arranged in a matrix. An output signal W0 to Wm transmitted from the X-decoder 16 is input into a gate of an associated memory cell of the memory cell array 10. A drain in each of memory cells is electrically connected to an associated digit line D0 to Dn, and a source in each of memory cells is electrically connected to a node CS. The node CS to which sources of the memory cells is electrically connected is kept at a ground voltage by a circuit (not illustrated) when data is read out of a memory cell.
The Y-selector 17 is comprised of MOSFETs QY0 to QYn each having a source electrically connected to each of digit lines D0 to Dn, a drain electrically connected to an input node SC through which the Y-selector 17 is electrically connected to the sense amplifier 18, and a gate electrically connected to each of output lines Y0 to Yn through which the Y-decoder 15 transmits its output signal to the Y-selector 17.
The sense amplifier 18 amplifies a voltage of a selected memory cell.
The reference cell MRD has a drain electrically connected to a node DR, a gate electrically connected to a reference cell selection signal line XR, and a source electrically connected to a node RS. The reference cell MRD has the same structure and characteristics as those of a memory cell arranged in the memory cell array 10. The node RS is kept at a ground (GND) voltage by a circuit (not illustrated) when data is read out of a selected memory cell.
The reference selector QR1 is comprised of a MOSFET having a drain electrically connected to a node RC through which the reference selector QR1 is electrically connected to the reference amplifier 19, a gate electrically connected to a reference cell selection signal line YR, and a source electrically connected to the node DR.
The voltages VR and VY are applied to the reference cell selection signal line XR and the reference cell selection signal line YR, respectively, when data is read out of a selected memory cell.
The reference amplifier 19 amplifies a voltage of the reference cell MRD.
The comparator-amplifier 20 amplifies a voltage difference between an output SA transmitted from the sense amplifier 18 and an output RA transmitted from the reference amplifier 19. The comparator-amplifier 20 judges whether a selected memory cell is in data-writing condition (0) or in data-erasing condition (1).
The output buffer 21 receives an output transmitted from the comparator-amplifier 20, and outputs data about a memory cell to an external data bus through an external output terminal I/O 0.
The semiconductor memory device illustrated in FIG. 1 actually has sixteen external output terminals I/O 0 to I/O 15 when the semiconductor memory device is designed to transmit a 16-bit output, for instance, and has sixteen sense amplifiers, memory cell arrays and comparator-amplifiers, accordingly. However, FIG. 1 illustrates only the external output terminal I/O 0 and its associated parts, and other external output terminals I/O 1 to I/O 15 and their associated parts are omitted for simplification. In addition, a control system and a power source system are omitted, because they have nothing to do with the present invention.
FIG. 2 illustrates waveforms of signals used for operating the conventional semiconductor memory device illustrated in FIG. 1. Symbols in FIG. 2 correspond to the nodes and signals illustrated in FIG. 1.
Hereinbelow is explained an operation of the semiconductor memory device on the assumption that a memory cell MC00 is selected for reading data out thereof.
In accordance with variance in the external address signal Ai, a word line W0 is selected, and thus, has a H level. The voltage VR is applied to the selected word line W0. Similarly, a Y-select line Y0 is selected, and thus, has a H level. The voltage VY is applied to the selected Y-select line Y0. As a result, the memory cell MC00 is selected.
In addition, in accordance with variance in the internal address signals Adi, the ATD circuit 13 transmits the address transition detecting signal P0 to the signal generating circuit 14, and then, the signal generating circuit 14 transmits the control signal P1 to the sense amplifier 18 and the reference amplifier 19 to thereby activate them.
Herein, it is assumed that a memory cell has a threshold voltage of 7V in the data-writing condition (0) and a threshold voltage of 2V in the data-erasing condition (1), and a reference cell has a threshold voltage of 3.4V. Data is read out of the selected memory cell MC00 as follows.
If the memory cell MC00 is in the data-writing condition (0), the memory cell MC00 does not allow a current to run therethrough, and resultingly, a voltage of the output SA transmitted from the sense amplifier 18 is lowered to a balanced voltage VSA(0) from an initial voltage V(ini), as shown with a waveform of a voltage SA(0).
On the other hand, the reference cell MRD allows a current to slightly run therethrough, and resultingly, a voltage of the output RA transmitted from the reference amplifier 19 is lowered to a balanced voltage VRA(i) from the initial voltage V(ini), as shown with a waveform of a voltage RA(i).
A voltage difference between the voltages VSA(O) and VRA(i) is amplified in the comparator-amplifier 20, and then, data stored in the memory cell is checked.
The comparator-amplifier 20 transmits its output to the output buffer 21, and the output buffer 21 transmits an output signal having a L level to an external output terminal I/Oi, as shown with a waveform of a voltage I/O 0(0).
If the selected memory cell MC00 is in the data-erasing condition (1), the memory cell MC00 allows a current to run therethrough, and resultingly, a voltage of the output SA transmitted from the sense amplifier 18 is lowered to a balanced voltage VSA(1) from the initial voltage V(ini), as shown with a waveform of a voltage SA(1).
On the other hand, the reference cell MRD allows a current to slightly run therethrough, and resultingly, a voltage of the output RA transmitted from the reference amplifier 19 is lowered to a balanced voltage VRA(i) from the initial voltage V(ini), as shown with a waveform of a voltage RA(i).
A voltage difference between the voltages VSA(1) and VRA(i) is amplified in the comparator-amplifier 20, and then, data stored in the memory cell is checked.
The comparator-amplifier 20 transmits its output to the output buffer 21, and the output buffer 21 transmits an output signal having a H level to an external output terminal I/Oi, as shown with a waveform of a voltage I/O 0(1).
As explained above, a H- or L-level signal is output to an external output terminal in accordance with a threshold level of a memory cell, and thus, data is read out of the semiconductor memory device.
In the conventional semiconductor memory device illustrated in FIG. 1, the 10-bit address signal Ai having addresses A10 to A19 is transmitted to the X-decoder 16. Hence, the X-decoder 16 has 1024 word lines (210=1024, “m” in FIG. 1 is equal to 1023). Accordingly, when data is read out of the memory cells in order, a time during which a voltage is applied to a word line is equal to 1/1024 of a time necessary for reading data out of all of the memory cells.
The reference cell MRD is always selected during data is read out of a memory cell regardless of which word line in the memory cell array 10 is selected, and hence, a voltage equal to the voltage VR applied to a selected word line is kept applied to the reference cell selection signal line XR of the reference cell MRD.
It is well known that a memory cell in a flash EEPROM is degraded after reading data out of the memory cell for a long time. It is obvious that a reference cell which is kept in a selected condition is first degraded, since a gate of the reference cell is biased by the data-reading voltage VR during data is read out of a memory cell.
The waveform RA(a) in FIG. 2 is a waveform of a reference voltage VR found after data-reading operation has been carried out for a long time (for instance, five years). As a result of carrying out data-reading operation long time, a reference cell is degraded, a current running therethrough is reduced. In addition, an initial voltage VRA(i) is raised up to a voltage VRA(a), resulting in that a gap between the voltages VRA(i) and VRA(a) is quite small. Thus, the comparator-amplifier 20 may wrongly operate. Specifically, as shown with a waveform I/O 0(0)a, a L-level voltage is not output to the external output terminal I/O 0, but a H-level voltage may be output to the external output terminal I/O 0.
As explained above, the conventional semiconductor memory device is accompanied with a problem that the reference cell MRD receives much stress in data-reading operation in comparison with the memory cells in the memory cell array 10, because the conventional semiconductor memory device is designed to include a single reference cell.
As a solution to the problem, Japanese Patent Application Publication No. 2001-250374 has suggested a semiconductor memory device which switches a reference cell to another in accordance with the number of operation of a reference cell. The suggested device is necessary to include at least a circuit for monitoring the number of operation of a reference cell, a circuit for detecting variance in characteristics of a reference cell, and a circuit for switching a dummy cell to a memory cell. As a result, the semiconductor memory device is unavoidably complicated in circuit structure, big in size, and high in cost.
Japanese Patent Application Publication No. 9-231775 has suggested a semiconductor memory device including a reference cell decoder for selecting a reference cell. However, a detailed structure of the reference cell decoder is not disclosed.
As mentioned above, a conventional semiconductor memory device including a reference cell for reading data out of, writing data into or erasing data out of a memory cell is accompanied with a problem of variance in characteristics of a reference cell. To solve such a problem, a semiconductor memory device has to include a lot of additional circuits, resulting in a problem of an increase in a size of a semiconductor memory device.
Japanese Patent Application Publication No. 11-144474 has suggested a non-volatile memory device including (a) a memory array including a plurality of memory cells each having a word line, a bit line, a cell electrode line associated with the word line, a ferroelectric capacitor, and a switching transistor, the ferroelectric capacitor having a first electrode electrically connected to an associated bit line through an associated switching transistor, and a second electrode electrically connected to an associated cell electrode line, the switching transistor having a control electrode electrically connected to an associated word line, (b) a detecting circuit receiving a level associated with a data bit of a selected memory cell, and a reference level defined as an average level of levels of associated data bits, and detecting a level of the selected data bit, and (c) a reference cell array including a plurality of reference cells each associated with each of the bit lines, and providing the reference level, the reference cell including at least one redundant cell associated with the bit line so that when the reference level is biased in one direction, the thus biased reference level is compensated for.
Japanese Patent Application Publication No. 11-185481 has suggested a semiconductor memory device including two pairs of bit lines. In each of pairs, variance in a voltage is generated in one of bit lines by means of data stored in a memory cell, and a reference voltage is generated in the other of bit lines by means of data stored in a reference cell. The two reference cells in each of pairs are electrically connected to each other through at least one transistor.
Japanese Patent Application Publication No. 2000-268558 has suggested a non-volatile ferroelectric memory device in which the number by which access is made to a main cell is made equal to the number by which access is made to a reference cell for lengthening a lifetime of the memory device.
Japanese Patent Application Publication No. 2001-6378 has suggested a semiconductor integrated circuit device including a non-volatile memory, a first register which reads data used for compensating for a reference voltage, out of the non-volatile memory, and stored the thus read-out data therein, a first circuit for compensating for a resistance thereof in accordance with the data stored in the first register, a second circuit for varying an output voltage in accordance with the resistance of the first circuit, and a control circuit for controlling operation of the non-volatile memory and the first register.
Japanese Patent Application Publication No. 2002-15562 has suggested a semiconductor memory device comprised of a one-transistor-and-one-capacitor type ferroelectric memory including a plurality of memory cells and a plurality of reference cells. Each of the reference cells is arranged separately from one another in association with each of the memory cells electrically connected to a common bit line. Each of the memory cells and each of the reference cells associated with each of the memory cells co-own a word line and a cell plate line.
Japanese Patent Application Publication No. 2002-15563 has suggested a circuit for generating a reference voltage in a ferroelectric memory including a ferroelectric capacitor as a memory cell. A plurality of reference memory cells each including a ferroelectric capacitor and a switch is electrically connected to a common reference bit line. Among the plurality of reference memory cells, first logic data is written into the predetermined number of the reference memory cells, and second logic data different from the first logic data is written into the rest of the reference memory cells. A reference voltage is generated in the reference bit line by selecting all of the reference memory cells.